Realization-independent ATPG for designs with unimplemented blocks

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 20; no. 2; pp. 290 - 306
• Main Authors: Hyungwon Kim, Hayes, J.P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Circuits; Computer aided design; Delay; Design engineering; Design methodology; Faults; Handles; Integrated circuit technology; Intellectual property; IP (Internet Protocol); Mathematical models; System testing; Test sets; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.908472

Conventional automatic test-pattern generation (ATPG) cannot effectively handle designs employing blocks whose implementation details are either unknown, unavailable, or subject to change. Realization-independent block testing for cores (RIBTEC), a novel ATPG program for such designs, is described, which employs a functional (behavioral) fault model based on a class of nonexhaustive "universal" test sets. Given a circuit's high-level block structure, RIBTEC constructs a universal test set (UTS) for each block from its functional description in such a way that realization independence of the blocks is ensured. Experimental results are presented for representative datapath circuits, which demonstrate that RIBTEC achieves very high fault coverage and an exceptionally high level of realization independence. We also show that RIBTEC can be applied to designs containing a class of small intellectual property (IP) circuits (cores).