Simultaneous gate sizing and placement

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 19; no. 2; pp. 206 - 214
• Main Authors: Wei Chen, Cheng-Ta Hseih, Pedram, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Circuits; Clocks; Delay; Design automation; Design optimization; Gates (circuits); Integrated circuit technology; Mathematical analysis; Mathematical models; Performance analysis; Placement; Simultaneous localization and mapping; Sizing; Time measurements; Timing; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.828549

This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform timing analysis to identify the set of k most-critical paths in the circuit followed by cell resizing and replacement along the critical path set and their neighboring cells. The process is repeated until no further reduction in circuit delay is possible. At the core of this technique lies a mathematical formulation for simultaneous cell sizing and placement subject to timing and position constraints. We show that the resulting problem formulation is a generalized geometric program, which can be solved by solving a sequence of geometric programs. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement.