Multibuffer delay line architectures for efficient contention resolution in optical switching nodes

• Published in: IEEE transactions on communications Vol. 48; no. 12; pp. 2089 - 2098
• Main Authors: Chlamtac, I., Fumagalli, A., Chang-Jin Suh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Computer science; Control systems; Costs; Delay lines; Fibers; Optical fiber networks; Optical packet switching; Optical propagation; Optical receivers; Optical switches; Optical switching; Photonics; Signal resolution; Storage capacity; Switches; Switching
• ISSN: 0090-6778; 1558-0857
• DOI: 10.1109/26.891219

This paper proposes an efficient contention resolution switching architecture which can serve as the basis for all-optical switching nodes. The presented solution builds on fiber delay lines used as temporary optical storage and 2/spl times/2 space photonic switches, a solution principle also known as Quadro or switched delay lines (SDLs). The efficiency of SDLs is fundamentally linked to its storage capacity, i.e., the length of the fiber delay lines, while its cost depends on the number of 2/spl times/2 photonic switches, i.e., the number of stages in the switch. This work presents a solution that makes use of multibuffer fiber delay lines which allow multiple packets to be concurrently stored (propagated) on each line. With a novel switch control, it is shown that this solution increases the total storage capacity and significantly improves switch and network performance, without increasing the number of the 2/spl times/2 switches in the system, i.e., its cost.