VLSI Implementation of Area and Power Efficient Digital Control Circuit for HF RFID Tag Chip

• Published in: Chinese Journal of Electronics Vol. 29; no. 1; pp. 82 - 88
• Main Authors: WANG, Deming, HU, Jianguo, WANG, Jianhui, DING, Yanyu, WU, Jing
• Format: Journal Article
• Language: English
• Published: Published by the IET on behalf of the CIE 01.01.2020
• Subjects: 2P6M CMOS process; bit rate 13.24 Gbit/s; bit rate 26.48 kbit/s; bit rate 26.69 kbit/s; bit rate 52.97 kbit/s; CMOS integrated circuits; control logic; Digital control circuit; field effect MMIC; HF RFID tag chip; high frequency RFID tag chip; integrated area efficient digital control circuit; integrated circuit design; ISO‐IEC 15693 protocol; Low power; low power circuit; low‐power electronics; Manchester encoder; power consumption; power efficient digital control circuit; pulse position modulation decoder; radiofrequency integrated circuits; RFID; RFID tag IC; size 0.18 mum; size 306.0 mum; size 326.0 mum; VLSI; VLSI implementation; ISO-IEC 15693 protocol; field effect MMIC; bit rate 52.97 kbit/s; pulse position modulation decoder; low power circuit; power consumption; size 306.0 mum; integrated area efficient digital control circuit; bit rate 26.48 kbit/s; high frequency RFID tag chip; integrated circuit design; CMOS integrated circuits; 2P6M CMOS process; size 0.18 mum; radiofrequency integrated circuits; VLSI; power efficient digital control circuit; bit rate 26.69 kbit/s; control logic; RFID; HF RFID tag chip; Low power; size 326.0 mum; bit rate 13.24 Gbit/s; RFID tag IC; Manchester encoder; VLSI implementation; low-power electronics; Digital control circuit
• ISSN: 1022-4653; 2075-5597
• DOI: 10.1049/cje.2019.10.003

A fully integrated area efficient digital control circuit based on the ISO/IEC 15693 protocol is proposed for high frequency RFID tag chip. The proposed circuit is mainly composed of pulse position modulation decoder, Manchester encoder, anticonllision, low power circuit and other control logic. It supports six different data rates, namely, low or high data rate with one subcarrier (6.62 or 26.48 Kbit/s), low or high data rate with two subcarriers (6.67 or 26.69 Kbit/s), fast data rate with one subcarrier (13.24 or 52.97 Kbit/s). The proposed digital control circuit was integrated in an RFID tag IC and was fabricated using a 0.18-µm 2P6M CMOS process with an area of 306µm by 326µm which is smaller than the existing designs. Besides of small area, the circuit has an advantage of low power with a power consumption of less than 50µW.