Hybrid HVDC circuit breakers with an energy absorption branch of a parallel arrester structure

• Published in: High voltage Vol. 7; no. 1; pp. 197 - 207
• Main Authors: Yu, Jingqiu, Xu, Zheng, Zhang, Zheren, Song, Yuanjian
• Format: Journal Article
• Language: English
• Published: Beijing John Wiley & Sons, Inc 01.02.2022; Wiley
• Subjects: Arresters; Basic converters; Circuit breakers; Electronic components; Energy; Energy absorption; Genetic algorithms; Hybrid circuits; Insertion; Modular structures; Overcurrent; Overvoltage; Parameters; Sorting algorithms; Switching; Zinc oxides
• ISSN: 2397-7264; 2397-7264
• DOI: 10.1049/hve2.12138

Hybrid circuit breakers (CBs) are the most promising technology to isolate DC faults in modular multilevel converter (MMC)‐based DC grids. However, they consist of expensive power electronic components that are sensitive to high overvoltage and overcurrent. This study proposes a hybrid high‐voltage DC circuit breaker with an energy absorption branch of a parallel arrester structure, and investigates the possibility of reducing the fault current and the switching overvoltage. First, the basic principle of an energy absorption branch with a parallel arrester structure is presented. Then, the simultaneous and sequential insertion strategies are illustrated. Second, each strategy and each structure are combined separately to analyse their respective characteristics in reducing the overvoltage, the fault current, the energy absorption and the fault clearance time. The sequential insertion strategy of the proposed energy absorption branch is proved to have the best performance. Finally, the trade‐offs between these four metrics are achieved through the non‐dominated sorting genetic algorithm II (NSGA‐II). A general method to determine the parameters of the proposed energy absorption branch from the Pareto front based on different preferences is provided. Simulations on PSCAD show that sequential insertion of the proposed energy absorption branch with the optimal parameters is able to suppress the switching overvoltage and limit the fault current to a relatively low extent simultaneously.