Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal--Oxide--Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process

The silicon nanowire gate-all-around (GAA) metal--oxide--semiconductor field effect transistors (MOSFETs) have been fabricated by using inverted sidewall spacers to scale the gate length. The patterning strategy of inverted sidewall spacers is based on the self-aligned local-channel V-shaped gate el...

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Bibliographic Details
Published inJapanese Journal of Applied Physics Vol. 49; no. 8; pp. 084203 - 084203-5
Main Authors Park, Jae Hyun, Song, Jae Young, Kim, Jong Pil, Kim, Sang Wan, Yun, Jang-Gn, Park, Byung-Gook
Format Journal Article
LanguageEnglish
Published The Japan Society of Applied Physics 01.08.2010
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Summary:The silicon nanowire gate-all-around (GAA) metal--oxide--semiconductor field effect transistors (MOSFETs) have been fabricated by using inverted sidewall spacers to scale the gate length. The patterning strategy of inverted sidewall spacers is based on the self-aligned local-channel V-shaped gate electrode (V-gate) by optical lithography (SALVO) process. Through this technique, we have obtained an aggressively scaled gate length down to 10 nm regime. In addition, the silicon nanowire structure with diameter of about 10 nm has been successfully formed by reducing of the local channel. In the fabricated device, we have confirmed that it has excellent device characteristics in terms of the sub-threshold swing (SS), drain induced barrier lowering (DIBL), and low level of off-state leakage current in spite of the short-channel effect (SCE).
Bibliography:(Color online) Schematic diagram and cross-section of the fabricated silicon nanowire GAA MOSFETs with important physical parameters. (Color online) Key process integration steps of the silicon nanowire GAA MOSFETs. (a) Active structure definition by following mix-and-match process. (b) Gate groove formation by use of e-beam lithography with ZEP520A e-beam resist. (c) Highly scaled gate line patterning through inverted sidewall spacers scheme of SALVO process. (d) BOX wet-etching and silicon nanowire formation by selective reduction method together with wet trimming process. (e) Gate oxidation and n + polysilicon gate deposition followed by etch-back process. (f) S/D As + ion implantation and RTA after removing dummy TEOS/nitride layers. (Color online) Cross-sectional SEM images. (a) Gate groove formation composed of dummy TEOS/nitride capping layers through e-beam lithography (108 nm groove width). (b) V-gate trench definition by the inverted nitride sidewall spacers of SALVO process (physical gate length of 20 nm). (Color online) SEM images of the BOX wet-etching by dipping in the $50:1$ BHF solution with 10 nm V-gate trench. The TEOS stack is protected by the nitride layers. (Color online) SEM images of the silicon nanowire structure. (a) The sharp corner still remains under the conventional oxidation process (800 \mbox{ \circ C} dry oxidation, normal SEM line pattern of $1\times 1$ um 2 ). But, the corner is rounded perfectly by applying our high temperature thermal oxidation condition and wet trimming method (cross-section of $130\times 40$ nm 2 ). (b) Precisely controlled silicon nanowire structure (wire diameter of 17 and 12 nm). (Color online) $I_{\text{D}}$--$V_{\text{G}}$ transfer characteristics of the fabricated silicon nanowire GAA MOSFETs. (Color online) $I_{\text{D}}$--$V_{\text{D}}$ output characteristics of the fabricated silicon nanowire GAA MOSFETs.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.49.084203