Single Electron Fault Modeling in Basic Quantum Devices

• Published in: Japanese Journal of Applied Physics Vol. 50; no. 9; pp. 094401 - 094401-5
• Main Authors: Mahdavi, Mojdeh, Mirzakuchaki, Sattar, Moghaddasi, Mohammad Naser, Amiri, Mohammad Amin
• Format: Journal Article
• Language: English
• Published: The Japan Society of Applied Physics 01.09.2011
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.50.094401

Quantum cellular automata represents an emerging technology at the nanotechnology level. There are various faults which may occur in quantum cellular automata cells. One of these faults is the single electron fault that can happen during manufacturing or operation of quantum cellular automata circuits. The behavior of single electron fault in quantum cellular automata devices is not similar to either previously investigated faults or conventional complementary metal oxide semiconductor (CMOS) logic. A detailed simulation based logic level modeling of single electron fault for quantum cellular automata binary wire and majority gate is represented in this paper. Results show that if a single electron fault occurs in a binary wire, the logic value of that wire will be inverted and if a single electron fault occurs in a majority gate, the logic value of that gate will be changed.