Large Memory Effect and High Carrier Mobility of Organic Field-Effect Transistors Using Semiconductor Colloidal Nano-Dots Dispersed in Polymer Buffer Layers
We fabricated organic memory field-effect transistors (FETs) using PbS colloidal nano-dots (NDs) dispersed in thin poly(methyl methacrylate) (PMMA) layers inserted between gate insulators (SiO 2 ) and pentacene active layers as floating gates. The colloidal NDs were dispersed in chloroform solution...
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| Published in | Japanese Journal of Applied Physics Vol. 50; no. 2; pp. 021601 - 021601-5 |
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| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
The Japan Society of Applied Physics
01.02.2011
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| Online Access | Get full text |
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| Summary: | We fabricated organic memory field-effect transistors (FETs) using PbS colloidal nano-dots (NDs) dispersed in thin poly(methyl methacrylate) (PMMA) layers inserted between gate insulators (SiO 2 ) and pentacene active layers as floating gates. The colloidal NDs were dispersed in chloroform solution with PMMA, and spin-coated on SiO 2 surfaces. The fabricated memory FETs showed significantly large threshold voltage shifts of 64.5 V at maximum after a writing voltage of 100 V was applied to their control gates, and a maximum carrier mobility of 0.36 cm 2 V -1 s -1 , which was comparable to that of reference pentacene FETs without colloidal NDs, was obtained because of the improved crystallinity of the pentacene films. |
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| Bibliography: | Schematic illustration of the memory FETs with PbS-ND:PMMA mixture layers fabricated in this study. XRD patterns of pentacene films deposited on the (a) CdSe/ZnS-ND monolayer, (b) PbS-ND:PMMA mixture layer, and (c) PMMA layer without colloidal NDs. AFM images of pentacene layer deposited on the (a) CdSe/ZnS-ND monolayer, (b) PMMA buffer layer, (c) PbS-ND:PMMA mixture layer. Histograms showing the distribution of carrier mobility of the (a) monolayer memory FETs, (b) reference FETs, and (c) memory FETs with PbS-ND:PMMA mixture layers. $(-I_{\text{D}})^{1/2}$--$V_{\text{G}}$ curves of the memory FET fabricated (a) without ND solution (reference FET) (b) with 0.02 wt % ND solution, and (c) with 0.04 wt % ND solution; dotted and solid lines are the curves measured before and after the writing voltage is applied, respectively. The gray arrows indicate the scan direction of the gate voltage. Transfer characteristics of the mixture-layer memory FET before writing (solid circles), after writing (solid line), and after erasing (open circles). It is demonstrated that the memory can be erased by applying a negative voltage of $-100$ V for 60 s on the control gate. The $V_{\text{th}}$ shift is measured at time intervals of 0--20 h between writing and reading; the retention time is longer than 20 h. A possible model for the energy band structure of the mixture-layer memory FET is schematically shown; it shows that the memory effect can be attributed to the electrons trapped in the NDs. |
| ISSN: | 0021-4922 1347-4065 |
| DOI: | 10.1143/JJAP.50.021601 |