NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

• Published in: IEEE journal of solid-state circuits Vol. 36; no. 3; pp. 522 - 527
• Main Authors: Miwa, T., Yamada, J., Koike, H., Toyoshima, H., Amanuma, K., Kobayashi, S., Tatsumi, T., Maejima, Y., Hada, H., Kunio, T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application specific integrated circuits; Backups; Capacitors; Circuits; EPROM; Fatigue; Ferroelectric films; Ferroelectric materials; Ferroelectricity; Flash memory; Nonvolatile memory; Random access memory; Static random access memory; Stores; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.910492

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.