Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

• Published in: Journal of low power electronics and applications Vol. 14; no. 1; p. 2
• Main Authors: Golman, Roman, Giterman, Robert, Teman, Adam
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.01.2024
• Subjects: 2R2W; 6R2W; Array processors; Availability; Data encryption; Design; dual-port; Graphics processing units; Machine learning; Memory (Computers); Memory management; Microprocessors; multi-port; N-ported; Power consumption; Random access memory; Static random access memory; System on chip; Transistors; two-port
• ISSN: 2079-9268; 2079-9268
• DOI: 10.3390/jlpea14010002

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.