Network-on-Chip interconnect for pairing-based cryptographic IP cores

On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with d...

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Bibliographic Details
Published inJournal of systems architecture Vol. 57; no. 1; pp. 95 - 108
Main Authors English, Tom, Popovici, Emanuel, Keller, Maurice, Marnane, W.P.
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 2011
Elsevier Sequoia S.A
Subjects
Buses (vehicles)
Circuits
CMOS
Computer architecture
Cryptography
Data transmission
Design engineering
Exchanging
Intellectual property
Interconnect
IP (Internet Protocol)
Network-on-Chip
Scalability
Studies
Tate Pairing
Weight reduction
Interconnect
Tate Pairing
Cryptography
Network-on-Chip
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Summary:On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are implemented on 65 nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wide cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1383-7621
1873-6165
DOI:10.1016/j.sysarc.2010.10.006