An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

• Published in: IEEE journal of solid-state circuits Vol. 36; no. 11; pp. 1758 - 1767
• Main Authors: Yoon, Chi-Weon, Woo, Ramchan, Kook, Jeengheon, Lee, Se-Joong, Lee, Kangmin, Yeo, Hoi-Jun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Circuits; Decoding; Dynamic random access memory; Energy consumption; Graphics; Hardware; Logic; Microprocessors; MPEG 4 Standard; Power consumption; Random access memory; Reduced instruction set computing; Rendering; Rendering (computer graphics)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.962299

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.