Capacitor model for a floating gate EEPROM cell

This paper presents a transient simulation model of a floating gate EEPROM cell based on the capacitor equivalent circuit of the device. The model is compared with a capacitor equivalent circuit model previously presented in the literature. The model is used to simulate the write and erase cycle tun...

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Bibliographic Details
Published inInternational journal of electronics Vol. 84; no. 6; pp. 561 - 581
Main Authors YANG, DAN, AXLEY, ROBERT S., DUEN HO, FAT
Format Journal Article
LanguageEnglish
Published London Taylor & Francis Group 01.06.1998
Taylor & Francis
Subjects
Applied sciences
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Integrated circuits
ROM
EEPROM memory
Capacitors
Modeling
Equivalent circuits
Floating gate MOS transistor
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Summary:This paper presents a transient simulation model of a floating gate EEPROM cell based on the capacitor equivalent circuit of the device. The model is compared with a capacitor equivalent circuit model previously presented in the literature. The model is used to simulate the write and erase cycle tunnel currents and the cell threshold voltages of two different EEPROM cells. The simulation results are compared with the experimentally measured tunnel currents and with the simulation results of the previously presented model.
ISSN:0020-7217
1362-3060
DOI:10.1080/002072198134418