Retention Benefit Based Intelligent Cache Replacement

The performance loss resulting from different cache misses is variable in modern systems for two reasons： 1） memory access latency is not uniform, and 2） the latency toleration ability of processor cores varies across different misses. Compared with parallel misses and store misses, isolated fetch a...

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Bibliographic Details
Published inJournal of computer science and technology Vol. 29; no. 6; pp. 947 - 961
Main Author 李凌达 陆俊林 程旭
Format Journal Article
LanguageEnglish
Published Boston Springer US 01.11.2014
Springer Nature B.V
Subjects
Aggregates
Artificial Intelligence
Computer Science
Core loss
Data Structures and Information Theory
Information Systems Applications (incl.Internet)
Mathematical models
Microprocessors
Policies
RBR
Regular Paper
Retention
Software Engineering
Stall
State of the art
Stores
Theory of Computation
处理器
性能损失
效益
智能
缓存替换
高速缓冲存储器
高速缓存
last-level cache
replacement
retention benefit
Online AccessGet full text
ISSN1000-9000
1860-4749
DOI10.1007/s11390-014-1481-2

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Summary:The performance loss resulting from different cache misses is variable in modern systems for two reasons： 1） memory access latency is not uniform, and 2） the latency toleration ability of processor cores varies across different misses. Compared with parallel misses and store misses, isolated fetch and load misses are more costly. The variation of cache miss penalty suggests that the cache replacement policy should take it into account. To that end, first, we propose the notion of retention benefit. Retention benefits can evaluate not only the increment of processor stall cycles on cache misses, but also the reduction of processor stall cycles due to cache hits. Then, we propose Retention Benefit Based Replacement （RBR） which aims to maximize the aggregate retention benefits of blocks reserved in the cache. RBR keeps track of the total retention benefit for each block in the cache, and it preferentially evicts the block with the minimum total retention benefit on replacement. The evaluation shows that RBR can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead. It also outperforms other state-of-the-art techniques.
Bibliography:retention benefit, replacement, last-level cache
11-2296/TP
The performance loss resulting from different cache misses is variable in modern systems for two reasons： 1） memory access latency is not uniform, and 2） the latency toleration ability of processor cores varies across different misses. Compared with parallel misses and store misses, isolated fetch and load misses are more costly. The variation of cache miss penalty suggests that the cache replacement policy should take it into account. To that end, first, we propose the notion of retention benefit. Retention benefits can evaluate not only the increment of processor stall cycles on cache misses, but also the reduction of processor stall cycles due to cache hits. Then, we propose Retention Benefit Based Replacement （RBR） which aims to maximize the aggregate retention benefits of blocks reserved in the cache. RBR keeps track of the total retention benefit for each block in the cache, and it preferentially evicts the block with the minimum total retention benefit on replacement. The evaluation shows that RBR can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead. It also outperforms other state-of-the-art techniques.
Ling-Da Li, Jun-Lin Lu, Xu Cheng （1Microprocessor Research and Development Center, Peking University, Beijing 100871, China 2Engineering Research Center of Microprocessor and System, Ministry of Education, Beijing 100871, China 3School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China）
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ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-014-1481-2