Current directions in automatic test-pattern generation

• Published in: Computer (Long Beach, Calif.) Vol. 32; no. 11; pp. 58 - 64
• Main Authors: Kwang-Ting Cheng, Krstic, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.1999; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Automatic test pattern generation; Automatic testing; Automation; Categories; Computer industry; DC generators; Debugging; Design automation; Design engineering; Design for testability; Faults; Handles; Information technology; Mathematical models; Pattern generation; Power generation; Scalability; Test pattern generators; Time measurements; Timing
• ISSN: 0018-9162; 1558-0814
• DOI: 10.1109/2.803642

Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in the article is on automatic test-pattern-generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification.