ASC: a stream compiler for computing with FPGAs

A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardware-design productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computer-aided...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 9; pp. 1603 - 1617
Main Author Mencer, O.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.09.2006
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Accelerators
Algorithms
Architecture
Arithmetic
Bridge circuits
Compilers
Cryptography
Data encryption
Design automation
Design space exploration
Field programmable gate arrays
FPGAs
Gates
Hardware
hardware design
Productivity
Program processors
Programming profession
Space exploration
Studies
Very large scale integration
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Summary:A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardware-design productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computer-aided-design (CAD) tools. ASC addresses this problem with a softwarelike programming interface to hardware design (FPGAs) while keeping the performance of hand-designed circuits at the same time. ASC improves productivity by letting the programmer optimize the implementation on the algorithm level, the architecture level, the arithmetic level, and the gate level, all within the same C++ program. The increased productivity of ASC is applied to the hardware acceleration of a wide range of applications. Traditionally, hardware accelerators are tediously handcrafted to achieve top performance. ASC simplifies design-space exploration of hardware accelerators by transforming the hardware-design task into a software-design process, using only "GNU compiler collection (GCC)" and "make" to obtain a hardware netlist. From experience, the hardware-design productivity and ease of use are close to pure software development. This paper presents results and case studies with optimizations that are: 1) on the gate level-Kasumi and International Data Encryption Algorithm (IDEA) encryptions; 2) on the arithmetic level-redundant addition and multiplication function evaluation for two-dimensional (2-D) rotation; and 3) on the architecture level-Wavelet and Lempel-Ziv (LZ)-like compression
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2005.857377