Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high perf...

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Bibliographic Details
Published inApplied sciences Vol. 10; no. 3; p. 748
Main Authors Kapoor, Dipesh, Tan, Cher Ming, Sangwan, Vivek
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 01.02.2020
Subjects
3d-ic (three-dimensional integrated circuit)
electromagnetic interference
Electromagnetism
Electrostatic discharges
Integrated circuits
Magnetic fields
near field measurement
Simulation
Transistors
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Summary:Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.
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ISSN:2076-3417
2076-3417
DOI:10.3390/app10030748