WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool

• Published in: SoftwareX Vol. 18; p. 101105
• Main Authors: Mariotti, Gianfranco, Giorgi, Roberto
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.06.2022; Elsevier
• Subjects: Computer architectures; Interactive learning environments; Pipeline computing; Simulation environments; Pipeline computing; Interactive learning environments; Computer architectures; Simulation environments
• ISSN: 2352-7110; 2352-7110
• DOI: 10.1016/j.softx.2022.101105

WebRISC-V is a web-based education-oriented tool, which permits the investigation of the pipelined execution of assembly programs according to the RV32IM and RV64IM specifications (32-bit or 64-bit RISC-V processor). The tool permits to evaluate and understand slow-downs in the execution due to pipeline stalls and further investigate the internal state of the pipeline architectural blocks (e.g., registers, memory, multiplexers, ALU). The pipeline concept is illustrated in the vast majority of university courses in Computer Architecture, since it is the well established standard for implementing high-performance processors. However, the impact of pipelined execution is often underestimated or even unknown, whilst it represents a very important source for the speed-up of programs. Several similar tools exist and are publicly available, but WebRISC-V is currently the first one that can be executed directly in a web-browser while displaying the cycle-by-cycle detailed pipeline execution for a RISC-V processor. This paper describes WebRISC-V, compares it against other similar available tools and presents its features. An example of usage for investigating the pipeline with the support of an automatically generated pipeline diagram is provided.