Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 26; no. 11; pp. 2023 - 2034
• Main Authors: Wong, E., Minz, J.R., Sung Kyu Lim
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Capacitors; Circuit faults; Decoupling; Decoupling capacitors (decaps); Devices; floorplanning; Integrated circuit noise; Integrated circuits; Jacobian matrices; Large scale integration; Leakage; Logic; Noise; Noise reduction; Power supplies; power-supply integrity; Sizing; Steady-state; Three dimensional; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2007.906463

Decoupling capacitors (decaps) are a popular means for reducing power-supply noise in integrated circuits. Since the decaps are usually inserted in the whitespace of the device layer, decap management during the floorplanning stage is desirable. However, a well-known existing work only allows the blocks to utilize the adjacent whitespace. In order to overcome this limit, we devise the effective-decap-distance model to analyze how functional blocks are affected by nonneighboring decaps. In addition, we propose a generalized network-flow-based algorithm to allocate the whitespace to the blocks and determine the oxide thicknesses for the decaps to be implemented in the whitespace. Experimental results show that our decap allocation and sizing methods can significantly reduce decap budget and leakage power with a small increase in area and wire length when integrated into 2D and 3D floorplanners.