Test generation and optimization for DRAM cell defects using electrical simulation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 22; no. 10; pp. 1371 - 1384
• Main Authors: Al-Ars, Z., van de Goor, A.J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Complexity; Computer simulation; Data storage; Design engineering; Design optimization; Faults; Memory devices; Optimization; Pattern analysis; Performance analysis; Performance evaluation; Process design; Random access memory; Stress; Studies; Test pattern generators; Testing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2003.818125

Although electrical simulation has become a vital tool in the design process of memory devices, memory testing has not yet been able to employ electrical simulation as an integral part of the test generation and optimization process. This is due to the exponential complexity of the simulation-based fault analysis, a complexity that made such an analysis impractical. This paper describes new methods to reduce the complexity of the fault analysis from exponential to constant with respect to the number of analyzed operations, thereby making it possible: 1) to use electrical simulation to generate test patterns; and 2) to perform simulation-based stress optimization of tests. The paper also discusses ways to analyze the impact of idle time on the faulty behavior. In addition, results of a fault analysis study performed to verify the new analysis method are shown, where the new analysis reduces the analysis time by a factor of 30.