Multiple channel programmable timing generators with single cyclic delay line

• Published in: IEEE transactions on instrumentation and measurement Vol. 53; no. 4; pp. 1295 - 1303
• Main Authors: Wang, T.-Y., Lin, S.-M., Tsao, H.-W.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automatic test equipment; Automatic testing; Calibration; Circuit testing; Counting circuits; Delay lines; Generators; Integrated circuits; Pulse generation; Space vector pulse width modulation; System testing; Test systems; Timing
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2004.830592

In this paper, we present the design and measurement results of multiple channel programmable timing generators (TGs) using single cyclic delay line for high-speed automatic test equipment (ATE) with 37.5 ps resolution and 5 ms programmable delay range. There are three TGs, and each one consists of a 19-bit 360-MHz count-up counter, a 19-bit cycle comparator, a zero cycle detector, a control word splitter, and an output selector with an 8X-interpolator. A 32-stage cyclic delay line is constructed via a pulsewidth self-controlled delay cell (PWSCDC). The proposed timing generator uses the TSMC 0.35 /spl mu/m 1P4M process with a die size of 2.33 mm /spl times/2.17 mm. The dynamic nonlinearity (DNL) is less than /spl plusmn/0.6 LSB (37.5 ps). The integral nonlinearity (INL) is between -1 LSB and 7 LSB before calibration, and is between /spl plusmn/0.4 LSB after root-mean-square (rms) value calibration. The multichannel phase mismatch (MCPM) is 19 ps (rms), and jitter is 13.7 ps (rms).