Application of the back-gate bias in MOSFET for a switch-type comparator in 4-b flash A D converter

• Published in: Microelectronics international Vol. 25; no. 3; pp. 14 - 18
• Main Authors: Cui, Zhi-Yuan, Kim, Yeong-Seuk, Choi, Moon-Ho, Lee, Hyung-Gyoo, Kim, Nam-Soo
• Format: Journal Article
• Language: English
• Published: Bradford Emerald Group Publishing Limited 01.01.2008; MCB University Press
• Subjects: Applied sciences; Circuit properties; Circuits; Design. Technologies. Operation analysis. Testing; Electric currents; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Optimization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Studies; Switching, multiplexing, switched capacity circuits; Transistors; Electronic engineering; Comparator circuits; Electric current; Ignition voltage; Analog circuit; Inverter; Voltage threshold; MOSFET; Power circuit; PMOS technology; Transfer characteristic; Power electronics; Voltage control; Optimal design; Flash converter; Power consumption; AD converter; Complementary MOS technology; Latch circuit; Sampling rate; Comparator circuit; Selector switch; Low-power electronics; Signal to noise and distortion ratio
• ISSN: 1356-5362; 1758-812X
• DOI: 10.1108/13565360810889575

Purpose - The purpose of this paper is to present the design and optimization of a comparator with two transistors.Design methodology approach - The effect of back-gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash-type A D converter (ADC). The 4-bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back-gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn-on voltage is controlled within 0.1 V in 4-bit ADC. The fabrication is done in a 0.35 μm single-poly four-metal process.Findings - Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.Originality value - A comparator which uses the effect of the back-gate bias on MOSFET is applied to a flash ADC. The paper is of value in showing how the circuit of this comparator is quite simple compared with a conventional comparator based on a CMOS latch, which is adaptable for a low-power analog circuit in future. The experimental output of the 4-bit flash ADC shows a good agreement with a simulation. Power consumption 1.2 mW, INL 0.2 LSB, and SNDR 25 dB are obtained in the simulation study.