Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the hi...

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Bibliographic Details
Published inApplied sciences Vol. 13; no. 18; p. 10360
Main Authors Zhang, Yi, Qiao, Lufeng, Hu, Lin, Xu, Xin, Chen, Qinghua
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 01.09.2023
Subjects
Algorithms
Artificial satellites
Bloom filter
Bridge/routers
CBHF
cuckoo filter
Digital integrated circuits
Embedded systems
Field programmable gate arrays
FPGA
Internet
Internet Protocol
Low earth orbit satellites
Memory (Computers)
PR-Trie
Routers
Satellite communications services industry
satellite IP route lookup
Transmission Control Protocol/Internet Protocol (Computer network protocol)
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Summary:The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.
ISSN:2076-3417
2076-3417
DOI:10.3390/app131810360