Analysis and performance evaluation of a three-phase sparse neutral point clamped converter for industrial variable speed drives

This paper analyzes the operation and characterizes the performance of a three-phase three-level (3-L) Sparse Neutral Point Clamped converter (SNPCC) for industrial variable speed drives (VSDs). The operating principle of the SNPCC, which advantageously employs a lower number of power transistors th...

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Bibliographic Details
Published inElectrical engineering Vol. 104; no. 2; pp. 623 - 642
Main Authors Cittanti, Davide, Guacci, Mattia, Mirić, Spasoje, Bojoi, Radu, Kolar, Johann Walter
Format Journal Article
LanguageEnglish
Published Berlin/Heidelberg Springer Berlin Heidelberg 01.04.2022
Springer Nature B.V
Subjects
Clamping
Converters
Cost analysis
Direct current
Economics and Management
Electrical Engineering
Electrical Machines and Networks
Energy Policy
Engineering
Modulation
Original Paper
Passive components
Performance evaluation
Phase current
Power Electronics
Power semiconductor devices
Semiconductors
Switching sequences
Topology
Transistors
Variable speed drives
Industrial variable speed drives
Sparse neutral point clamped converter
Silicon IGBT
Semiconductor chip area
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Summary:This paper analyzes the operation and characterizes the performance of a three-phase three-level (3-L) Sparse Neutral Point Clamped converter (SNPCC) for industrial variable speed drives (VSDs). The operating principle of the SNPCC, which advantageously employs a lower number of power transistors than a conventional 3-L inverter, is described in detail, focusing on the AC-side differential-mode and common-mode voltage formation and on the DC-side mid-point current generation processes. The degrees of freedom in the SNPCC modulation scheme are defined and several switching sequences are investigated. Afterwards, the stresses on the active and passive components (e.g. semiconductor losses, machine phase current ripple, DC-link capacitor RMS current, etc.) are calculated by analytical and/or numerical means, enabling a straightforward performance comparison among the identified switching sequences. The most suited modulation strategy for VSD applications is then selected and a chip area sizing procedure, aimed at minimizing the total semiconductor chip size, is applied to a 800V 7.5kW three-phase system. The performance limits of the designed SNPCC are evaluated and finally compared to the ones of conventional 2-L and 3-L solutions, highlighting the promising cost/performance trade-off of the analyzed topology.
ISSN:0948-7921
1432-0487
DOI:10.1007/s00202-021-01290-w