3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures

• Published in: IEEE electron device letters Vol. 35; no. 6; pp. 660 - 662
• Main Authors: Lin, Leo Jyun-Hong, Chiou, Yih-Peng
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2014; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D-ICs; Applied sciences; Capacitance; Couplings; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; guarding structures; Integrated circuits; Noise; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; semiconductor physics; substrate coupling; Substrates; Threshold voltage; through-silicon via (TSV); Through-silicon vias; transients; Transistors; semiconductor physics; substrate coupling; 3-D-ICs; through-silicon via (TSV); transients; guarding structures; Electromagnetism; Semiconductor materials; Noise reduction; Guard ring; Reduction method; Interconnection; Integrated circuit; Silicon; Circuit noise; Copper; Transient analysis; Via hole
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2014.2318301

Substrate coupling in 3-D-ICs using Cu through silicon vias (TSVs) is a predicament widely documented in recent literature. Yet, discussions remain limited to the electromagnetic framework, such that a complete understanding of noise propagation and absorption is hampered. This letter thoroughly examines these phenomena in the TSVs from the integrated perspectives of semiconductor physics and electromagnetic theory and investigates the noise reduction method using the combination of p+ guard-ring and grounded TSV via 3-D device simulation.