A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model con...

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Bibliographic Details
Published inChinese physics B Vol. 19; no. 12; pp. 530 - 536
Main Author 朱樟明 郝报田 杨银堂 李跃进
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.12.2010
Subjects
CMOS工艺
互补金属氧化物半导体
互连线
时延模型
电路优化
约束模型
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Summary:Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
Bibliography:interconnect power, repeater area, low-swing circuit, time delay, bandwidth
TP391.75
TP391.72
11-5639/O4
ISSN:1674-1056
2058-3834
DOI:10.1088/1674-1056/19/12/127805