A high performance MQ encoder architecture in JPEG2000

In this paper, a novel architecture for an MQ arithmetic coder with high throughput is proposed. The architecture can process two symbols in parallel. The main characteristics are eight process elements for the prediction of probability interval A, the combination of calculation units for the code r...

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Bibliographic Details
Published inIntegration (Amsterdam) Vol. 43; no. 3; pp. 305 - 317
Main Authors Liu, Kai, Zhou, Yu, Song Li, Yun, Ma, Jian Feng
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 01.06.2010
Elsevier
Subjects
Applied sciences
Architecture
Arithmetic
Circuit properties
Coders
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Encoders
Exact sciences and technology
Mathematical analysis
MQ encoder
Process elements
Registers
Signal convertors
Symbols
Tables (data)
MQ encoder
Process elements
High performance
Coding
Coding circuit
Image compression
Field programmable gate array
Implementation
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Summary:In this paper, a novel architecture for an MQ arithmetic coder with high throughput is proposed. The architecture can process two symbols in parallel. The main characteristics are eight process elements for the prediction of probability interval A, the combination of calculation units for the code register C with the Byteout&Flush procedure, and the use of a dedicated probability estimation table to decrease the internal memory. From FPGA synthesis results, the architecture’s throughput can reach 96.60 M context symbols per second with an internal memory size of 1509 bits, which is comparable to that of other architectures and suitable for chip implementation.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2010.01.001