Performance-driven mapping for CPLD architectures

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 22; no. 10; pp. 1424 - 1431
• Main Authors: Deming Chen, Cong, J., Ercegovac, M., Zhijun Huang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Arrays; Circuits; Computer science; Delay; Design engineering; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Logic devices; Mapping; Microelectronics; Programmable logic arrays; Programmable logic devices; Table lookup
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2003.818120

We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.