A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

• Published in: Measurement science & technology Vol. 20; no. 2; pp. 025108 - 025108 (11)
• Main Authors: Szplet, R, Kalisz, J, Jachna, Z
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.02.2009
• ISSN: 0957-0233; 1361-6501
• DOI: 10.1088/0957-0233/20/2/025108

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.