Quadruple throughput fixed point quarter precision multiply accumulate circuit design

• Published in: Chronic diseases and translational medicine Vol. 11; no. 5; pp. 183 - 189
• Main Authors: Mohamed Asan Basiri, M, Noor Mohammad, S.k
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.09.2017; John Wiley & Sons, Inc
• Subjects: array multiplier‐based double throughput MAC; Array processors; CMOS integrated circuits; CMOS TSMC library; Design; digital arithmetic; Digital signal processors; fixed point quarter precision multiply accumulate circuit design; integrated circuit design; MAC designs; MAC operations; quadruple throughput; Research Article; VLSI; VLSI architecture; array multiplier-based double throughput MAC; quadruple throughput; MAC operations; CMOS TSMC library; VLSI; digital arithmetic; integrated circuit design; fixed point quarter precision multiply accumulate circuit design; MAC designs; VLSI architecture; CMOS integrated circuits
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2017.0051

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.