Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 1; pp. 159 - 172
• Main Authors: Yin, Xunzhao, Chen, Xiaoming, Niemier, Michael, Hu, Xiaobo Sharon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accumulators; Associative memory; Capacitance; Circuits; CMOS; Computer architecture; Delay; Equivalence; Ferroelectric FET (FeFET); Ferroelectric materials; Ferroelectricity; Field effect transistors; Iron; Logic; logic-in-memory (LiM); Magnetic tunneling; Mathematical model; MOSFET; nonvolatile (NV) memory; Power consumption; Random access; Semiconductor devices; Tunnel junctions
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2871119

Among the beyond-complementary metal-oxide-semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic <inline-formula> <tex-math notation="LaTeX">I_{\text {ds}} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">V_{\text {gs}} </tex-math></inline-formula> characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine-grained logic-in-memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs), resistive random access memories (ReRAMs), ferrorelectric tunnel junctions (FTJs), etc., that afford the same circuit-level functionality. Simulation results show that FeFET-based NV TCAMs offer lower area overhead than MTJ (79%) and CMOS (42% less) equivalents, as well as better search energy-delay products (EDPs) than TCAM designs based on MTJ (<inline-formula> <tex-math notation="LaTeX">149\times </tex-math></inline-formula>), ReRAM (<inline-formula> <tex-math notation="LaTeX">1.7\times </tex-math></inline-formula>), and CMOS (<inline-formula> <tex-math notation="LaTeX">1.3\times </tex-math></inline-formula>) in array evaluations. NV FeFET-based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay (<inline-formula> <tex-math notation="LaTeX">4.2\times </tex-math></inline-formula>) and dynamic power (<inline-formula> <tex-math notation="LaTeX">2.5\times </tex-math></inline-formula>). A case study for an FeFET-based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET-based accumulator can save area (36%) and power consumption (40%) when compared with a conventional CMOS accumulator with the same structure.