A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 69; no. 3; pp. 1672 - 1676
• Main Authors: Della Sala, Riccardo, Bellizia, Davide, Scotti, Giuseppe
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Art exhibits; Computer architecture; Entropy; field programmable gate array (FPGA); Field programmable gate arrays; Jitter; Latches; metastability; Oscillators; Random numbers; ring oscillators; Table lookup; Throughput; TRNGs; Vibration
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2021.3121537

In this brief we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.