Automated Driving of GaN Chireix Power Amplifier for the Digital Predistortion Linearization

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 68; no. 6; pp. 1887 - 1891
• Main Authors: Galaviz-Aguilar, Jose Alejandro, Vargas-Rosales, Cesar, Tlelo-Cuautle, Esteban
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Automation; behavioral modeling; Chireix; cubic spline; Delays; digital predistortion; GaN; Linearity; Linearization; Multiaccess communication; Phase measurement; power amplifier; Power amplifiers; Power generation; Radio frequency; Table lookup
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2020.3040659

This brief presents the measurement/modeling of a dual-input outphasing Chireix power amplifier (PA) for the analysis of nonlinear and memory effects behavior when excited with modulated signals. Moreover, we formulate a cubic-spline (CS) memory model with a closed-loop for the digital predistortion (DPD) linearization algorithm. An FPGA system has been developed to automate the outphasing angles and their respective asymmetrical incident power levels applied at the Class-F PAs of the Chireix under test. Based on experimental results, the CS model offers a DPD with a normalized mean square error (NMSE) of −21.87 dB, and −52.47 dB for a WCDMA 5-MHz and an LTE-A 10-MHz with −26.84 dB and −43.91 dB in extraction and prediction, respectively. An output power improvement of −43.5 dBc in adjacent channel power ratio (ACPR) with 9.3 dB PAPR yield 50% average efficiency enhance at 2 GHz, is achieved.