Detection and Coding Schemes for Sneak-Path Interference in Resistive Memory Arrays

• Published in: IEEE transactions on communications Vol. 67; no. 6; pp. 3821 - 3833
• Main Authors: Ben-Hur, Yuval, Cassuto, Yuval
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; bhattacharyya bound; Coding; Computer architecture; Computer memory; detection; Detectors; Electrical resistance measurement; Encoding; Error detection; Interference; Memristor; Resistance; Resistors; sneak-path
• ISSN: 0090-6778; 1558-0857
• DOI: 10.1109/TCOMM.2019.2897762

Resistive memory is a promising technology for achieving unprecedented storage densities and new in-memory computing features. However, to fulfill their promise, resistive memories require array architectures suffering from a severe interference effect called "sneak paths." In this paper, we address the sneak-path problem through a communication-theory framework. Starting from the fundamental problem of readout with parallel-resistance interference, we develop several tools for detection and coding that significantly improve memory reliability. For the detection problem, we formulate and derive the optimal detector for a realistic array model, and then propose simplifications that enjoy similarly good performance and simpler implementation. Complementing detection for better error rates is done by a new coding scheme that shapes the stored bits to get lower sneak-path incidence. For the same storage rates, the new coding scheme exhibits error rates lower by an order of magnitude compared to known shaping techniques.