A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People

Deep convolutional neural network (DCNN) object detection is a powerful solution in visual perception, but it requires huge computation and communication costs. We proposed a fast and low-power always-on object detection processor that allows visually impaired people to understand their surroundings...

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Bibliographic Details
Published inIEEE transactions on circuits and systems for video technology Vol. 29; no. 11; pp. 3444 - 3453
Main Authors Chen, Xiaobai, Xu, Jinglong, Yu, Zhiyi
Format Journal Article
LanguageEnglish
Published New York IEEE 01.11.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Algorithms
Artificial neural networks
assist system
Computational efficiency
Computer simulation
Data transfer (computers)
DCNN
Energy efficiency
Energy management
Hardware
Indexes
Lookup tables
low-bit
Microprocessors
Multilayers
multiplierless
Object detection
Object recognition
Optimization
People with disabilities
Performance indices
Power
Power management
Quantization (signal)
Visual impairment
Visual perception
visually impaired people
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Summary:Deep convolutional neural network (DCNN) object detection is a powerful solution in visual perception, but it requires huge computation and communication costs. We proposed a fast and low-power always-on object detection processor that allows visually impaired people to understand their surroundings. We designed an automatic DCNN quantization algorithm that successfully quantizes the data to 8-bit fix-points with 32 values and uses 5-bit indexes to represent them, reducing hardware cost by over 68% compared to the 16-bit DCNN, with negligible accuracy loss. A specific hardware accelerator is designed, which uses reconfigurable process engines to realize multi-layer pipelines to significantly reduce or eliminate the off-chip temporary data transfer. A lookup table is used to implement all multiplications in convolutions to reduce the power significantly. The design is fabricated in SMIC 55-nm technology, and the post-layout simulation shows only 68-mw power at 1.1-v voltage with 155 Go/s performance, achieving 2.2 Top/w energy efficiency.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2018.2883087