Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

• Published in: IEEE transactions on nanotechnology Vol. 18; pp. 999 - 1004
• Main Authors: Razavieh, Ali, Zeitzoff, Peter, Nowak, Edward J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS; CMOS Scaling; Computer architecture; Contact resistance; Contact Resistivity; Contacted-Gate-Pitch (CGP); Electrostatics; Fin-Pitch; FinFET; FinFETs; Logic gates; Moore's Law; Performance evaluation; Scaling; VLSI Technology
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2019.2942456

Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP ~ 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (ρ C ) of ~8 × 10 -10 Ω-cm 2 , while fully ohmic contacts i.e., ρ C of ~1 × 10 -10 Ω-cm 2 will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.