Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 9; no. 3; pp. 525 - 535
• Main Authors: Melamed, Samson, Imura, Fumito, Nakagawa, Hiroshi, Kikuchi, Katsuya, Hagimoto, Michiya, Matsumoto, Yukoh, Aoyagi, Masahiro
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.03.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Chip formation; Chips; Data buses; Field programmable gate arrays; Integrated circuit interconnections; integrated circuit testing; Integrated circuits; Interconnections; Performance evaluation; Power demand; Stacking; Test procedures; Three-dimensional displays; three-dimensional integrated circuits; Through-silicon vias
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2018.2873298

In this paper, we present "Cool Interconnect," a 1024-bit wide bus that we have developed to provide a standardized method of interconnecting chips in 3-D integrated circuits (3DICs). This wide bus chip-to-chip interconnect can be used to realize low-power high-performance multicore systems to meet the increasing demand for advanced electronics to enable autonomous vehicles and Internet of Things devices. The bus has been implemented using a <inline-formula> <tex-math notation="LaTeX">40\times 40 </tex-math></inline-formula> fine-pitch array of through-silicon vias and bump joints. In addition, we have developed a testing methodology based on the boundary scan method to confirm the electrical performance of wide bus chip-to-chip interconnect in 3DICs. Cool Interconnect test chips were designed, fabricated, and flip-chip stacked. Joint Test Action Group (JTAG) and electrical connection tests were used to confirm the successful operation of the test chips, including the chip-to-chip interconnect.