Versatile multiplier architectures in GF ( 2 k ) fields using the Montgomery multiplication algorithm

• Published in: Integration (Amsterdam) Vol. 41; no. 3; pp. 371 - 384
• Main Authors: Fournaris, Apostolos P., Koufopavlou, O.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.05.2008; Elsevier Science
• Subjects: Applied sciences; Circuit properties; Computations in finite fields; Computer arithmetic; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Montgomery multiplication; Pipeline; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Versatile design; VLSI; Versatile design; Computations in finite fields; Montgomery multiplication; VLSI; Computer arithmetic; Pipeline; Performance evaluation; Finite field; Arithmetic circuit; VLSI circuit; Clock; Algorithm; Optimization; Latch circuit; Integrated circuit; Multiplier; Critical path; High frequency
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2007.07.004

Many sequential multipliers for polynomial basis GF ( 2 k ) fields have been proposed using the LSbit and MSbit multiplication algorithm. However, all those designs are defined over fixed size GF ( 2 k ) fields and sometimes over fixed special form irreducible polynomials (AOL, trinomials, pentanomials). When such architectures are redesigned for arbitrary GF ( 2 k ) fields and generic irreducible polynomials, therefore made versatile, they result in high space complexity (gate–latch number), low frequency (high critical path) and high latency designs. In this paper a Montgomery multiplication element (MME) architecture specially designed for arbitrary GF ( 2 k ) fields defined over general irreducible polynomials, is proposed, based on an optimized version of the Montgomery multiplication (MM) algorithm for GF ( 2 k ) fields. To evaluate the proposed MME and prove the efficiency of the MM algorithm in versatile designing, three distinct versatile Montgomery multiplier architectures are presented using this proposed MME. They achieve small gate–latch number and high clock frequency compared to other sequential versatile designs.