Highly parallel scanning tunneling microscope based hydrogen depassivation lithography

• Published in: Journal of vacuum science and technology. B, Nanotechnology & microelectronics Vol. 36; no. 6
• Main Authors: Randall, John N., Owen, James H. G., Lake, Joseph, Saini, Rahul, Fuchs, Ehud, Mahdavi, Mohammad, Moheimani, S. O. Reza, Schaefer, Benjamin Carrion
• Format: Journal Article
• Language: English
• Published: United States American Vacuum Society 01.11.2018
• ISSN: 2166-2746; 2166-2754
• DOI: 10.1116/1.5047939

Hydrogen depassivation lithography (HDL) carried out by a scanning tunneling microscope has sub-nm resolution and the potential to create atomically precise patterns. However, as a serial write tool, it is subject to Tennant’s law which fairly accurately predicts an extremely low areal throughput in line with their experimental results. In order to improve the throughput, the authors explore the feasibility of an approach to develop a highly parallel exposure system, which preserves the ability to perform truly atomically precise patterning. The obvious way to increase scanning probe lithography throughput is to increase the number of probes. In this paper, they compare existing multiple scanning probe systems [D. S. Ginger, H. Zhang, and C. A. Mirkin, Angew. Chem. Int. Ed. 43, 30 (2004) and P. Vettiger et al., Microelectronic 46, 11 (1999)] with their proposed highly parallel, MEMS-based scanners with three degrees of freedom (3 DoF) movement. Additionally, since HDL is a version of e-beam lithography, they examine the problems encountered by the attempts to go parallel with conventional e-beam lithography and why highly parallel HDL avoids these physical and engineering problems. While there are still some engineering challenges to be met, the path to massively parallel HDL tip arrays is relatively straightforward. They believe that 3 DoF MEMS-based independently controlled scanners could be placed with a density of 10 100/cm2. That density range implies 7 × 106 tips on a 300 mm wafer. However, they do want to make clear that they do not contend that even this level of parallelism will make HDL a contender for producing CMOS consumer electronics.