Electrical and reliability characterization of CuMn self forming barrier interconnects on low-k CDO dielectrics

PVD CuMn self-forming barrier (SFB) approach was investigated on 300mm wafers as an alternative to conventional PVD Ta/Cu metallization. Cu fill on very aggressive dual damascene features targeted for beyond 32nm node was evaluated along with integrated electrical and reliability performance on low-...

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Published inMicroelectronic engineering Vol. 92; pp. 49 - 52
Main Authors Indukuri, Tejaswi K., Akolkar, Rohan N., Clarke, James S., Genc, Arda, Gstrein, Florian, Harmes, Michael C., Miner, Barbara, Xia, Feng, Zierath, Daniel J., Balakrishnan, Sridhar
Format Journal Article Conference Proceeding
LanguageEnglish
Published Amsterdam Elsevier B.V 01.04.2012
Elsevier
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Summary:PVD CuMn self-forming barrier (SFB) approach was investigated on 300mm wafers as an alternative to conventional PVD Ta/Cu metallization. Cu fill on very aggressive dual damascene features targeted for beyond 32nm node was evaluated along with integrated electrical and reliability performance on low-k (k=2.6) interlayer dielectric (ILD).
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2011.04.043