Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

Binary addition and multiplication problems are very important as their time dominates computation time of any scientific or engineering problem. Simple algorithms are presented for these 2 problems which take only O(1) time and O(log n) time on a linear PARBS and n x 2n-PARBS respectively, in which...

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Bibliographic Details
Published inInformation processing letters Vol. 46; no. 2; pp. 89 - 94
Main Authors Thangavel, P., Muthuswamy, V.P.
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 17.05.1993
Elsevier Science
Elsevier Sequoia S.A
Subjects
Algorithms
Applied sciences
Binary addition
Distributed computer systems
Electronics
Exact sciences and technology
Hardware
Information processing
Integrated circuits
Mathematical models
multiplication
parallel algorithms
reconfigurable bus
Theory
parallel algorithms
multiplication
Binary addition
reconfigurable bus
Addition
Parallel algorithm
Multiplication
Parallelism
Reconfigurable bus
Parallel computer
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Summary:Binary addition and multiplication problems are very important as their time dominates computation time of any scientific or engineering problem. Simple algorithms are presented for these 2 problems which take only O(1) time and O(log n) time on a linear PARBS and n x 2n-PARBS respectively, in which each processor has only a constant number of gates and registers. It is believed that these algorithms could be an efficient design for the implementation of an adder and multiplier circuit in a single VLSI chip.
ISSN:0020-0190
1872-6119
DOI:10.1016/0020-0190(93)90203-L