Trans-capacitance modeling in junctionless gate-all-around nanowire FETs

• Published in: Solid-state electronics Vol. 96; pp. 34 - 37
• Main Authors: Jazaeri, Farzan, Barbut, Lucian, Sallese, Jean-Michel
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier Ltd 01.06.2014; Elsevier
• Subjects: AC analysis; Applied sciences; Circuits; Compact model; Computer aided design; Computer simulation; Cross-disciplinary physics: materials science; rheology; Devices; Electronics; Exact sciences and technology; Gate-all-around; Gates; Junctionless; Materials science; Mathematical analysis; Molecular electronics, nanoelectronics; Nanoscale materials and structures: fabrication and characterization; Nanowire; Nanowires; Physics; Quantum wires; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Three dimensional; Trans-capacitance; Transistors; Nanowire; AC analysis; Compact model; Junctionless; Trans-capacitance; Gate-all-around; Circuit design; Small signal behavior; Small signal; Compact design; GAA transistor; Modeling; Nanoelectronics; Field effect transistor; Nanowire device; Analytical method; Capacitance; Nanowires; Computer aided design
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2014.04.022

•Junctionless nano-wire is one of the most promising alternative architecture for CMOS.•Some works have been done via numerical simulations.•An analytical and explicit model of trans-capacitance matrix is investigated in this work.•This paper is an important stage to include AC analysis in junctionless nanowire FETs. In this brief, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme recently pointed out between JL NW FET and its double gate counterpart for which such a model has been proposed. This approach is validated by 3D Technology Computer Aided Design simulations and bridges the gap between the nanowire junctionless device and its application in circuits.