Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Sch...

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Published inETRI journal Vol. 30; no. 3; pp. 347 - 354
Main Authors Lee, Jae‐Hyung, Kim, Ji‐Hong, Lim, Gyu‐Ho, Kim, Tae‐Hoon, Lee, Jung‐Hwan, Park, Kyung‐Hwan, Park, Mu‐Hun, Ha, Pan‐Bong, Kim, Young‐Hee
Format Journal Article
LanguageEnglish
Published 한국전자통신연구원 01.06.2008
Subjects
charge pump
dual power
EEPROM
Low‐power
sensing scheme
tag chip
UHF RFID
전자/정보통신공학
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Summary:In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
G704-001110.2008.30.3.002
ISSN:1225-6463
2233-7326
DOI:10.4218/etrij.08.0107.0154