High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications
In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current ( I ds ) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency ( fT ) and...
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Published in | IEEE electron device letters Vol. 33; no. 10; pp. 1477 - 1479 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.10.2012
Institute of Electrical and Electronics Engineers |
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Abstract | In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current ( I ds ) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency ( fT ) and maximum oscillation frequency ( f MAX ) along with 65% improvement in voltage gain ( A VO ) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors. |
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AbstractList | In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current ( I ds ) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency ( fT ) and maximum oscillation frequency ( f MAX ) along with 65% improvement in voltage gain ( A VO ) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors. |
Author | Kranti, A. Parihar, M. S. Armstrong, G. A. Ghosh, D. |
Author_xml | – sequence: 1 givenname: D. surname: Ghosh fullname: Ghosh, D. organization: Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. (IIT) Indore, Indore, India – sequence: 2 givenname: M. S. surname: Parihar fullname: Parihar, M. S. organization: Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. (IIT) Indore, Indore, India – sequence: 3 givenname: G. A. surname: Armstrong fullname: Armstrong, G. A. organization: Sch. of Electron., Electr. Eng. & Comput. Sci., Queens Univ. Belfast, Belfast, UK – sequence: 4 givenname: A. surname: Kranti fullname: Kranti, A. email: akranti@iiti.ac.in organization: Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. (IIT) Indore, Indore, India |
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Keywords | Analog circuit MOS technology High performance MOSFET Circuit design Oscillation frequency Analog/RF Dual gate transistor Optimization Nanoelectronics Cut off frequency Junctionless transistor Drain current underlap source/drain (S/D) double-gate MOSFET ultralow power (ULP) Low-power electronics Comparative study Gain junctionless (JL) transistor |
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SubjectTerms | Analog circuits Analog/RF Applied sciences Capacitance Circuit properties Cutoff frequency double-gate MOSFET Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology junctionless (JL) transistor Logic gates Molecular electronics, nanoelectronics MOSFETs Performance evaluation Radio frequency Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors ultralow power (ULP) underlap source/drain (S/D) |
Title | High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications |
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