High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications

• Published in: IEEE electron device letters Vol. 33; no. 10; pp. 1477 - 1479
• Main Authors: Ghosh, D., Parihar, M. S., Armstrong, G. A., Kranti, A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2012; Institute of Electrical and Electronics Engineers
• Subjects: Analog circuits; Analog/RF; Applied sciences; Capacitance; Circuit properties; Cutoff frequency; double-gate MOSFET; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; junctionless (JL) transistor; Logic gates; Molecular electronics, nanoelectronics; MOSFETs; Performance evaluation; Radio frequency; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; ultralow power (ULP); underlap source/drain (S/D); Analog circuit; MOS technology; High performance; MOSFET; Circuit design; Oscillation frequency; Analog/RF; Dual gate transistor; Optimization; Nanoelectronics; Cut off frequency; Junctionless transistor; Drain current; underlap source/drain (S/D); double-gate MOSFET; ultralow power (ULP); Low-power electronics; Comparative study; Gain; junctionless (JL) transistor
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2012.2210535

In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current ( I ds ) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency ( fT ) and maximum oscillation frequency ( f MAX ) along with 65% improvement in voltage gain ( A VO ) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors.