Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

• Published in: IEEE electron device letters Vol. 33; no. 3; pp. 315 - 317
• Main Authors: Markov, S., Binjie Cheng, Asenov, A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; CMOS integrated circuits; Correlation; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fully depleted silicon-on-insulator (SOI); Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; MOSFETs; random dopant fluctuations; Resource description framework; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; statistical device variability; Threshold voltage; Transistors; Voltage threshold; MOS technology; Static random access memory; MOSFET; statistical device variability; Fully depleted silicon-on-insulator (SOI); Random access memory; Depletion layer; Short channel; Compact design; Silicon on insulator technology; Non volatile memory; Statistical model; Integrated circuit; Standard deviation; Low-power electronics; random dopant fluctuations
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2011.2179114

Simulations of up to 10 000 fully depleted thin-body silicon-on-insulator MOSFETs show that the standard deviation of the threshold voltage cannot be adequately used as a sole metric of device variability in such transistors. This is due to a sharp departure from normality of the threshold voltage distribution, and an enhanced influence of the source/drain-dopant fluctuations on the on-current and short-channel effects of the fully depleted thin-body silicon-on-insulator transistors. Both aspects have great ramifications for statistical compact models and for low-power SRAM designs.