Dissecting GPU Memory Hierarchy Through Microbenchmarking

• Published in: IEEE transactions on parallel and distributed systems Vol. 28; no. 1; pp. 72 - 86
• Main Authors: Mei, Xinxin, Chu, Xiaowen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Benchmark testing; Benchmarks; cache structure; Computer architecture; Computer memory; CUDA; GPU; Graphics processing units; Hardware; Hierarchies; Instruction sets; Kernel; memory hierarchy; Throughput
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2016.2549523

Memory access efficiency is a key factor in fully utilizing the computational power of graphics processing units (GPUs). However, many details of the GPU memory hierarchy are not released by GPU vendors. In this paper, we propose a novel fine-grained microbenchmarking approach and apply it to three generations of NVIDIA GPUs, namely Fermi, Kepler, and Maxwell, to expose the previously unknown characteristics of their memory hierarchies. Specifically, we investigate the structures of different GPU cache systems, such as the data cache, the texture cache and the translation look-aside buffer (TLB). We also investigate the throughput and access latency of GPU global memory and shared memory. Our microbenchmark results offer a better understanding of the mysterious GPU memory hierarchy, which will facilitate the software optimization and modelling of GPU architectures. To the best of our knowledge, this is the first study to reveal the cache properties of Kepler and Maxwell GPUs, and the superiority of Maxwell in shared memory performance under bank conflict.