In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

• Published in: IEEE journal of solid-state circuits Vol. 52; no. 4; pp. 915 - 924
• Main Authors: Jintao Zhang, Zhuo Wang, Verma, Naveen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Algorithms; Analog computation; Arrays; Boosting; Circuits; Classifiers; Computational modeling; Computer architecture; Discrete systems; Image classification; image detection; in-memory computation; Machine learning; Machine learning algorithms; Prototypes; Random access memory; Signal classification; Static random access memory; Training
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2642198

This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model. Peripheral circuits implement mixed-signal weak classifiers via columns of the SRAM, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns. A prototype 128 × 128 SRAM array, implemented in a 130-nm CMOS process, demonstrates ten-way classification of MNIST images (using image-pixel features downsampled from 28 × 28 = 784 to 9 × 9 = 81, which yields a baseline accuracy of 90%). In SRAM mode (bit-cell read/write), the prototype operates up to 300 MHz, and in classify mode, it operates at 50 MHz, generating a classification every cycle. With accuracy equivalent to a discrete SRAM/digital-MAC system, the system achieves ten-way classification at an energy of 630 pJ per decision, 113× lower than a discrete system with standard training algorithm and 13× lower than a discrete system with the proposed training algorithm.