A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB
This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the...
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| Published in | Journal of semiconductors Vol. 34; no. 8; pp. 172 - 176 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.08.2013
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/34/8/085015 |
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| Abstract | This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied. |
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| AbstractList | This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter (ADC) in 0.18 mu m CMOS process with a 1.8 V supply voltage. A fast foreground digital calibration mechanism is employed to correct capacitor mismatches. The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio (SNDR) and an 87.5 dB spurious-free dynamic range (SFDR) with a 30.7 MHz input signal, while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input. The power consumption is 543 mW and a total die area of 3 x 4 mm super(2) is occupied. This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied. |
| Author | 王科 范超杰 周健军 潘文捷 |
| AuthorAffiliation | Centre for Analog/Radio Frequency Integrated Circuits （CARFIC）, Shanghai Jiao Tong University, Shanghai 200240, China |
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| Cites_doi | 10.1109/4.121557 10.1109/4.261994 10.1109/JSSC.2009.2032636 10.1109/TCSI.2004.836842 10.1109/JSSC.2004.836232 10.1088/1674-4926/33/2/025012 10.1109/4.826813 10.1088/1674-4926/33/2/025010 10.1109/JSSC.1987.1052843 |
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| DocumentTitleAlternate | A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB |
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| Notes | This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied. pipelined ADC SHA-less MDAC residue amplifier digital calibration 11-5781/TN Wang Ke, Fan Chaojle, Zhou Jianjun, and Pan Wenjie Centre for Analog/Radio Frequency Integrated Circuits （CARFIC）, Shanghai Jiao Tong University, Shanghai 200240, China ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
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| References | Ali A (1) 2010; 45 Ali A M A (13) 2006; 41 Razavi B (7) 2000 Cai Hua (10) 2012; 33 2 Luo L (12) 2009 3 4 5 6 Zhao Lei (11) 2012; 33 8 9 |
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| Snippet | This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground... This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter (ADC) in 0.18 mu m CMOS process with a 1.8 V supply voltage. A fast foreground... |
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| SubjectTerms | ADC Calibration Capacitors CMOS CMOS工艺 Distortion Noise levels Power consumption Semiconductors SFDR Voltage 数转换器 流水线 电源电压 输入信号 |
| Title | A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB |
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