A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB

This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 8; pp. 172 - 176
Main Author 王科 范超杰 周健军 潘文捷
Format Journal Article
LanguageEnglish
Published 01.08.2013
Subjects
ADC
Calibration
Capacitors
CMOS
CMOS工艺
Distortion
Noise levels
Power consumption
Semiconductors
SFDR
Voltage
数转换器
流水线
电源电压
输入信号
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ISSN1674-4926
DOI10.1088/1674-4926/34/8/085015

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Summary:This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.
Bibliography:This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio（SNDR） and an 87.5 dB spurious-free dynamic range（SFDR） with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.
pipelined ADC SHA-less MDAC residue amplifier digital calibration
11-5781/TN
Wang Ke, Fan Chaojle, Zhou Jianjun, and Pan Wenjie Centre for Analog/Radio Frequency Integrated Circuits （CARFIC）, Shanghai Jiao Tong University, Shanghai 200240, China
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SourceType-Scholarly Journals-1
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ISSN:1674-4926
DOI:10.1088/1674-4926/34/8/085015